Changes by last author:
Changed:
| This is the primary fuel injection system, not as fully featured as the V3 but smaller and able to communicate with the other VEMSFrontier boards |
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To avoid confusion, I propose that in the future
* armefi codename is reserved for the high-end board, likely SAAB70 connector * VemsFrontier/ArmUfo will be used for EC36 based controller, still awesome featureset Significant part of the development effort is shared. This is the primary fuel injection system. Smaller than v3.x and able to communicate with the other VEMSFrontier boards |
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Trigger is also directly connected to an ADC channel. An ADC (of 2) is appr. 364ksps but sweeping over 8 channels means only 45 ksps per channel. Perfect for knock and IonSense but trigger needs double samplerate. IIRC it is not possible to automatically (using PDC for transferring samples to memory) sample in arbitrary order (eg, 0,1,2,3,4,0,1,5,6,7 ), because the "conversion sequencer" can only go in sequence of the ADC_CHSR enabled channels (someone please confirm):
* that means same primary_trigger signal will be connected to 2 channels (eg ch0 and ch4 of the same ADC block) but we have to check again. |
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First, trigger is clamped in HW. Than
* Trigger is shaped with LM1815 and connected to an input capture. This allows trigging on falling edge, at negative crossingh of 0V * Trigger is sent to another input capture without shaping with LM1815 first so both edges can be trigged on. * Trigger is also directly connected to an ADC channel. This allows analyze the signal with a simple algorithm (similar to what LM1815 does in analog, but more flexible this way) and perhaps send to log (to PC or MMC) when necessary An ADC (of 2) is appr. 364ksps but sweeping over 8 channels means only 45 ksps per channel. Perfect for knock and IonSense but trigger needs double samplerate. IIRC it is not possible to automatically (using PDC for transferring samples to memory and minimizing interrupt overhead) sample in arbitrary order (eg, 0,1,2,3,4,0,1,5,6,7 ), because the "conversion sequencer" can only go in sequence of the ADC_CHSR enabled channels (someone please confirm): * that means same primary_trigger signal could be connected to 2 channels (eg ch0 and ch4 of the same ADC block) but we have to check again. |
| I don't think we need both channels. You're right about the ordering, but it seems to me that the "conversion sequencer" is only used when using the ADC while the processor is asleep. We can still use the PDC and change the sampled channels when we get the transfer complete interrupt (e.g. 0, 1, 2, 3 4, interrupt, 0, 1, 5, 6, 7 , interrupt ). What suggests that 0, 1, 5, 6, 7 is possible? if so, why is 0,1,2,3,4,0,1,5,6,7 not possible? |
| I don't think we need both channels. You're right about the ordering, but it seems to me that the "conversion sequencer" is only used when using the ADC while the processor is asleep. We can still use the PDC and change the sampled channels when we get the transfer complete interrupt (e.g. 0, 1, 2, 3 4, interrupt, 0, 1, 5, 6, 7 , interrupt ). This means 75k interrupt / sec that was ruled out earlier. However, it might work (with a fast, highly optimized assembly handler). Also, the trigger and knock/IonSense can be sampled with high freq, and the other channels just enabled for a run once in a while when necessary. The added code complexity due to non-even sampling should not be prohibitive. |
| Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. |
| Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. |
| ECIII 36 pin mapping: |
| ECIII 36 pin mapping: - for armufo |