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'''Chip design basics and how it affects Density, Speed, Power consumption and cost''' Lets consider that there is a fixed cost per waver of base material processed. Therefore the number of working chips per waver defines the base for the price. The latest technology always has a slight premium cost because of yield and development cost. We usually see the latest technology pioneered in the dynamic ram market. There the feature size or better its square is pushing the limits (=> Photolithography)Today the highest density (1Gbit DRAM chip, [http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 Xilinx] & [http://www.altera.com/products/devices/stratix2/st2-index.jsp Altera] FPGA) is produced in 90nm technology. http://www.aeiveos.com/~bradbury/petaflops/siardmap.html Reduced feature size has two further effects: one needs to reduce the voltage to assure that those electrons remain in their tunnel, in turn the speed increases that is because of lower intrinsic capacities (smaler surface), lower currents (less cap. & less voltage) and because of shorter average run length. That’s why the latest CPU's and DRAM work with ~1.5V but operate at GHz frequencies. The FPGA Technology suggested for the GoBox project (Altera Cyclone Family) is still implemented in a 130nm process using 1.5 V and supporting frequencies above 500 MHz internally. If a CPU uses 5 or 3.3 Volts it likely uses older well established mainstream technology. That means the cost per waver may be somewhat smaller but the chip size in turn bigger. Top speeds are limited Power consumption is a limit for maximal chip size or number of transistors that can operate in parallel. That means you will currently find the highest speed processors made with 1.5 V cores (and usually 3.3V IO). see FPGAProContra. I hope this clears some uncertainties.
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